Yes on both accounts. Conventional SDRAM memory feeds the CPU, then waits
for the CPU to respond back before it moves on to the next task. DDR cache
can feed the CPU while the CPU simultaneously sends the memory its completed
task. Think of it as a two way street (DDR) as opposed to a one way street
Aspen Systems, Inc.
Phone: 800-992-9242 Ext: 117
----- Original Message -----
From: "Eugene Chu" <firstname.lastname@example.org>
Sent: Tuesday, November 07, 2000 3:25 PM
Subject: Re: API Networks article on The Register
> I wrote:
> >Any idea why the new faster CPU (833 MHz) has only 4 MB of cache while
> >the previous CPU had 8 MB? It seems that faster CPUs would need more L1
> >cache in order to be able to keep running faster.
> Which should have been L2 cache.
> And Maurice W. Hilarius replied:
> >The memory bus front side bus speed on a UP2K is 83MHz.
> >With the 667 it was memory bus speed time 8.
> >With the 750 it "featured" a multiplier of 10 times 75MHz. So the memory
> >fsb was running at 75MHz, and the larger 8MB cache was needed to keep it
> >full speed.
> >With the 833 it is running a 10x multiplier of 83, plus it is DDR cache,
> >giving an effective cache access speed that is twice as fast as the older
> >CPU modules.
> and later Tom Heibel wrote:
> >DDR cache is a Double Data Rate cache memory. In laymans terms, it is
> >a bi-directional memory chip. This means it can accomplish the same
> >speed and better latency than a system with twice as much non DDR
> So let me state what I think is what I understand:
> The DDR cache is a bi-directional memory that can provide twice the
> data rate as non-DDR cache. So does this mean it can do both read and
> write simultaneously? Does this also mean that the non-DDR cache
> memories had to split its clock cycles between reads and writes?
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